1. Field of the Invention
The present invention relates to a ferroelectric random access memory device, and in particular, to a data read circuit.
2. Description of the Related Art
A memory device having a one-transistor/one-capacitor ferroelectric memory cell is given as one example of a ferroelectric random access memory device. The one-transistor/one-capacitor ferroelectric memory cell memory device includes one charge transfer gate MOS transistor and one ferroelectric capacitor, which are series-connected. Various types are given as a data read circuit for reading data from the ferroelectric memory cell. In general, the ferroelectric capacitor has a hysteresis characteristic between voltage and charge relationship. The following document has disclosure that when an imprint phenomenon occurs in hysteresis characteristic, a signal of data “1”/“0” read to a bit line from the ferroelectric memory cell changes.
Document: S. Kawashima, T. Endo, A. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita and M. Aoki, “Bitline GND sensing technique for low-voltage operation FeRAM”, IEEE Journal of Solid-State Circuits, volume: 37, Issue: 5, May 2002, pp. 592-598.
On the other hand, there has been known a charge transfer type as the data read circuit of the conventional ferroelectric memory device. The charge transfer type data read circuit transfers a charge read from the ferroelectric memory cell to a bit line to a sense amplifier via a transfer PMOS transistor and coupling capacitor.
The charge transfer type data read circuit has almost no signal change by the imprint phenomenon occurring in the ferroelectric capacitor. In particular, when the ferroelectric capacitor having ideal parallelogram hysteresis characteristic (loop), there is almost no generation of signal change by the imprint phenomenon. However, the data read circuit has a need to generate a negative voltage supplied to the gate of a charge transfer PMOS transistor. In addition, the structure adaptable to the negative voltage must be employed. For this reason, the circuit configuration and process become troublesome.
Moreover an output data of the sense amplifier connected to the bit line is inverted with respect to data read from the memory cell to the bit line. For this reason, circuit connection and control for writing and rewiring the output data of the sense amplifier to the memory cell become complicated.
A double bit line type data read circuit also proposed, which is disclosed in JPN. PAT. APPLN. KOKAI Publication No. 2002-32984. In the foregoing ferroelectric memory device, a sub-bit line connected with several ferroelectric memory cells is connected to the bit line via a current mirror circuit. A data read circuit of the ferroelectric memory device has the following configuration. More specifically, a pair of current input nodes of a first current mirror circuit is connected correspondingly to a first sub-bit line and a first bit line. Likewise, a pair of current input nodes of a second current mirror circuit is connected correspondingly to a second sub-bit line and a second bit line. The voltage of the first and second bit lines is supplied to a pair of input nodes of the sense amplifier.
However, in also case of the double bit line type data read circuit, the output data of the sense amplifier connected to the bit line is inverted with respect to data read from the memory cell to the bit line. For this reason, circuit connection and control for rewriting the output data of the sense amplifier to the memory cell become complicated.